`timescale 1ns / 1ps
module BUS_EN_DECODE (
    input in_ACC_in_en,
    input in_ACC_out_en,

    input in_BR_in_en,
    input in_BR_out_en,

    input in_MR_in_en,
    input in_MR_out_en,

    input in_Rx_in_en,
    input in_Rx_out_en,

    input in_SP_in_en,
    input in_SP_out_en,
    //输出控制信号
    output out_ACC_in_en,
    output out_ACC_out_en,  

    output out_BR_in_en,
    output out_BR_out_en,

    output out_MR_in_en,
    output out_MR_out_en,
   
    output out_AX_in_en,
    output out_AX_out_en, 
    output out_BX_in_en,
    output out_BX_out_en,
    output out_CX_in_en,
    output out_CX_out_en,
    output out_DX_in_en,
    output out_DX_out_en,

    output out_SP_in_en,
    output out_SP_out_en,
    //Rx寄存器寻址序号
    input [2:0]Rx_in_index,//Rx_in序号[9:7]
    input [2:0]Rx_out_index//Rx_out序号[6:4]//来自IR
);

`define ACC_index 3'b000
`define BR_index  3'b001
`define MR_index  3'b010
`define AX_index  3'b011
`define BX_index  3'b100
`define CX_index  3'b101
`define DX_index  3'b110
`define SP_index  3'b111

assign out_ACC_in_en = in_ACC_in_en || (in_Rx_in_en && (Rx_in_index == `ACC_index));
assign out_BR_in_en = in_BR_in_en || (in_Rx_in_en && (Rx_in_index == `BR_index));
assign out_MR_in_en = in_MR_in_en || (in_Rx_in_en && (Rx_in_index == `MR_index));
assign out_SP_in_en = in_SP_in_en || (in_Rx_in_en && (Rx_in_index == `SP_index));
assign out_AX_in_en = in_Rx_in_en && (Rx_in_index == `AX_index);
assign out_BX_in_en = in_Rx_in_en && (Rx_in_index == `BX_index);
assign out_CX_in_en = in_Rx_in_en && (Rx_in_index == `CX_index);
assign out_DX_in_en = in_Rx_in_en && (Rx_in_index == `DX_index);

assign out_ACC_out_en = in_ACC_out_en || (in_Rx_out_en && (Rx_out_index == `ACC_index));
assign out_BR_out_en = in_BR_out_en || (in_Rx_out_en && (Rx_out_index == `BR_index));
assign out_MR_out_en = in_MR_out_en || (in_Rx_out_en && (Rx_out_index == `MR_index));
assign out_SP_out_en = in_SP_out_en || (in_Rx_out_en && (Rx_out_index == `SP_index));
assign out_AX_out_en = in_Rx_out_en && (Rx_out_index == `AX_index);
assign out_BX_out_en = in_Rx_out_en && (Rx_out_index == `BX_index);
assign out_CX_out_en = in_Rx_out_en && (Rx_out_index == `CX_index);
assign out_DX_out_en = in_Rx_out_en && (Rx_out_index == `DX_index);
    
endmodule